The present invention relates to a charge pump circuit, and more particularly to a high speed charge pump circuit having a field effect transistor possessing an improved charge transfer efficiency.
As non-volatile memories, electrically erasable programmable read only memory and flash memories have been known. It is necessary for erasing and programming processes to apply high voltages to the memories. Such high voltages are generated in the non-volatile memory, wherein a charge pump circuit is accommodated in the non-volatile memory.
FIG. 1 is a circuit diagram illustrative of one of the conventional charge pump circuits, wherein the conventional charge pump circuit is operated with two-phase clock signals and has n-type MOS field effect transistors and capacitors. The first conventional charge pump circuit has a series connection of n-type MOS field effect transistors M0, M1, M2, M3, M4 . . . Mn, wherein each of the n-type MOS field effect transistors M0, M1, M2, M3, M4 . . . Mn has a gate electrode and a drain electrode which are connected to each other. The n-type MOS field effect transistors M0, M1, M2, M3, M4 . . . Mn are connected in series through nodes P1, P2, P3, P4 . . . Pn-1. The drain electrode of the first stage n-type MOS field effect transistor M0 is connected through a node P0 to a high voltage line Vcc which is connected to a power supply such as a battery. A source of the final stage n-type MOS field effect transistor Mn is connected through a final stage output node Pn to an output terminal of the charge pump circuit. The nodes P1, P2, P3, P4 . . . Pn-1 are also connected to first terminals of capacitors C1, C2, C3, C4 . . . Cn-1. The capacitors C1, C2, C3, C4 . . . Cn-1 have second terminals which receive two-phase clock signals #1 and #2. FIG. 2 is a diagram illustrative of waveforms of the two-phase clock signals #1 and #2 to be inputted into the second terminals of the capacitors C1, C2, C3, C4 . . . Cn-1 of the first conventional charge pump circuit illustrated in FIG. 1. Each of the first phase clock signal #1 and the second phase clock signal #2 is alternately inputted into the capacitors C1, C2, C3, C4 . . . Cn-1. Namely, the first phase clock signal #1 is inputted into the odd number stage capacitors C1, C3, . . . , whilst the second phase clock signal #2 is inputted into the even number stage capacitors C2, C4, The charges are transferred from the smaller number stage node Pi through the MOS field effect transistor Mi to the larger number stage node Pi+1, whereby the voltage level is increased. Consequently, the charges supplied via the high voltage line Vcc are transferred through the nodes P1, P2, P3, P4 . . . Pn and the n-type MOS field effect transistors M0, M1, M2, M3, M4 . . . Mn into the final stage node Pn+1, whereby the voltage level is increased up to the predetermined and required high voltage level. The conventional charge pump circuit further has transistor diodes D1, D2, D3, D4 . . . Dn which are connected in series between the high voltage line Vcc and the nodes P1, P2, P3, P4 . . . Pn respectively. Gates and drains of the transistor diodes D1, D2, D3, D4 . . . Dn are connected to the high voltage line Vcc whilst sources of the transistor diodes D1, D2, D3, D4 . . . Dn are connected to the nodes P1, P2, P3, P4 . . . Pn respectively, so that the drains of the n-type MOS field effect transistors M1, M2, M3, M4 . . . Mn are applied with voltages of Vcc-Vtd1, Vcc-Vtd2, Vcc-Vtd3, Vcc-Vtd4, where Vtdi is the threshold voltage of the transistor diode Di.
The above conventional charge pump circuit has the following disadvantages. For example, it is now considered that the charge is transferred through the MOS field effect transistor M2. Assuming that the initial voltages or potentials of the nodes P2 and P3 are Vp2 and Vp3 respectively, if the first phase clock #1 is low level whilst the second phase clock #2 is high level, then the n-type MOS field effect transistor M2 turns ON, whereby the charge transfer through the n-type MOS field effect transistor M2 is made. Since the gate and drain of the n-type MOS field effect transistor M2, then the gate of the n-type MOS field effect transistor M2 is applied with a voltage level of Vp2+{Ci/(Ci+Cj)}Vcc, where Ci is the capacitance of the capacitor Ci and Cj is the parasitic capacitance of the node Pi. Therefore, the voltage or potential Vp3 of the node P3 may be increased to a maximum value of Vp2+{Ci/(Ci+Cj)}Vcc-Vtm, where Vtm is the threshold voltage of the n-type MOS field effect transistors M0, M1, M2, M3, M4 . . . Mn. This shows an inefficient charge transfer. Thereafter, the voltage level or potential Vp2 of the node P2 is decreased with the charge transfer, whereby the efficiency of the charge transfer is further dropped.
In Japanese laid-open patent publication No. 7-111095, a more efficient second conventional charge pump circuit is disclosed. FIG. 3 is a circuit diagram illustrative of the second conventional charge pump circuits, wherein the second conventional charge pump circuit is operated with four-phase clock signals and has n-type MOS field effect transistors and capacitors in addition boosting up MOS field effect transistors. The second conventional charge pump circuit has a series connection of n-type MOS field effect transistors M0, M1, M2, M3, M4 . . . Mn. The n-type MOS field effect transistors M0, M1, M2, M3, M4 . . . Mn are connected in series through nodes P1, P2, P3, P4 . . . Pn. The drain electrode of the first stage n-type MOS field effect transistor M0 is connected through a node P0 to a high voltage line Vcc which is connected to a power supply. A source of the final stage n-type MOS field effect transistor Mn is connected through a final stage output node Pn+1 to an output terminal of the charge pump circuit. The second conventional charge pump circuit also has n-type boost-up MOS field effect transistors N0, N1, N2, N3, N4 . . . Nn which are connected in series between the nodes P0, P1, P2, P4 . . . Pn and gates of the n-type MOS field effect transistors M0, M1, M2, M3, M4 . . . Mn. The second conventional charge pump circuit has capacitors C0, C1, C2, C3, C4, C5, C6, C7, C8 . . . C2n. The capacitors C0, C1, C2, C3, C4, C5, C6, C7, C8 . . . C2n have first terminals and second terminals which receive four-phase clock signals #1, #2, #3 and #4. The nodes P1, P2, P3, P4 . . . Pn are also connected to the first terminals of the odd number stage capacitors C1, C3, C5, C7 . . . C2n-1. The odd number stage capacitors C1, C3, C5, C7 . . . C2n-1 have second terminals which receive the first and third phase clock signals #1 and #3 alternately. The first terminals of the even number stage capacitors C0, C2, C4, C6, C8 . . . C2n are connected to gates of the n-type MOS field effect transistors M0, M1, M2, M3, M4 . . . Mn. The even number stage capacitors C0, C2, C4, C6, C8 . . . C2n have second terminals which receive the second and fourth phase clock signals #2 and #4 alternately. The n-type boost-up MOS field effect transistors N0, N1, N2, N3, N4 . . . Nn have gates which are connected to the next stage nodes P1, P2, P3, P4, P5 . . . Pn+1. Those next stage nodes P1, P2, P3, P4, P5 . . . Pn+1 are also connected to the first terminals of the odd number stage capacitors C1, C3, C5, C7 . . . C2n-1 having the second terminals which receive the first and third phase clock signals #1 and #3 alternately. The second conventional charge pump circuit further has transistor diodes D1, D2, D3, D4 . . . Dn which are connected in series between the high voltage line Vcc and the nodes P1, P2, P3, P4 . . . Pn respectively. Gates and drains of the transistor diodes D1, D2, D3, D4 . . . Dn are connected to the high voltage line Vcc whilst sources of the transistor diodes D1, D2, D3, D4 . . . Dn are connected to the nodes P1, P2, P3, P4 . . . Pn respectively. FIG. 4 is a diagram illustrative of waveforms of the individual nodes P1, P2, P3, P4 . . . Pn of the second conventional charge pump circuit in operation as illustrated in FIG. 3.
When the time is T1, the individual nodes P1, P2, P3, P4 . . . Pn have voltages Vp1(T1), Vp2(T1), Vp3(T1), Vp4(T1), . . . Vpn(T1). The second and fourth phase clock signals #2 and #4 are in the low level. The gates of the n-type boost-up MOS field effect transistors N0, N1, N2, N3, N4 . . . Nn are connected to the next stage nodes P1, P2, P3, P4, P5 . . . Pn+1, for which reason the voltages Vp1(T1), Vp2(T1), Vp3(T1), Vp4(T1), . . . Vpn(T1) of the individual nodes P1, P2, P3, P4 . . . Pn are applied to the gates of the n-type boost-up MOS field effect transistors N0, N1, N2, N3, N4 . . . Nn. The gates of the n-type MOS field effect transistors M0, M1, M2, M3, M4 . . . Mn have voltages Vq0(T1), Vq1(T1), Vq2(T1), Vq3(T1), Vq4(T1), . . . Vqn(T1) respectively.
When the charge pump circuit is in the initial state of the boost-up process or where the drain of the transistor is connected to the high voltage line, the following equation is given. EQU Vpn+1(T1)-Vpn(T1)&gt;Vtn
where Vtn is a threshold voltage of the transistor Ni.
Therefore, Vqn(T1)=Vpn(T1) is given.
In the middle and later time periods of the boost-up process or in the initial time pried of the boost-up process, the transistor on the output side stage has voltage relationships defined by the following equation.
Vpn+1(T1)-Vpn(T1)&lt;Vtn
Therefore, Vpn(T1)=Vpn+1(T1)-Vtn is given.
When the time is T2, the first phase clock signal #1 is low level, and the voltage levels Vp1(T2) and Vp3(T2) are dropped to the following levels respectively. EQU Vp1(T1)-{Ci/(Ci+Cj)}Vcc EQU Vp3(T)-{Ci/(Ci+Cj)}Vcc
When the time is T3, then the fourth phase clock signal #4 is high level, and the voltage levels Vq0(T3) and Vq2(T3) are given as follows respectively. EQU Vq0(T1)+{Ck/(Ck+Cg)}Vcc EQU Vq2(T1)+{Ck/(Ck+Cg)}Vcc
where Ck is the capacitance of the capacitors connected to the gates of the transistors M0 . . . Mn, and Cg is the parasitic capacitance of nodes Q0, Q1, Q2, Q3, Q4, . . . Qn which are connected to the gates of the transistors M0 . . . Mn respectively.
The gate voltage of the second conventional charge pump circuit is higher than that of the first conventional charge pump circuit by about {Ck/(Ck+Cg)}Vcc. This means that the four phase clock signal second conventional charge pump circuit shows more efficient charge transfer than the two phase clock signal first conventional charge pump circuit.
When the time is T4, the fourth phase clock signal #4 is low level, whereby all of the transistors M0 . . . Mn turn OFF.
When the time is T5, then the voltage levels Vp1(T5), Vp3(T5) are risen whereby the second conventional charge pump circuit enters into the same operation as when the time is T1 but different in phase by 180 degrees therefrom.
The above sequential operations of the second conventional charge pump circuit are repeated so that the charges are transferred to the final stage node Pn+1 connected to the source of the final stage transistor Mn, whereby the final stage node Pn+1 has the required voltage level.
The above second conventional charge pump circuit has the following disadvantages. Even the potential of the output stage is risen, in the time period between T1 and T2, a maximum potential difference between the voltage levels Vpn(T1) and Vpn+1(T1) is only Vcc, for which reason a small amount of charges is transferred to the node Qn(T1), whereby the voltage levels of the nodes Q0 . . . On connected to the gate voltages of the transistors M0 . . . Mn show almost no rise, and thus only an additional voltage level added in additional boosting up can be effected to transfer the charge to the output side.
In the above circumstances, it had been required to develop a novel charge pump circuit free from the above problems or disadvantages.